SoftRank: 6.82 |
A constraint- and design-rule driven interactive and fully automatic shape-based router. It supports block authoring and chip authoring solutions for designs at any level of the hierarchy. |
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SoftRank: 6.82 |
Analyzes the combined impact of major noise sources including crosstalk, IR drop, and propagated noise on the design for custom digital circuits. |
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SoftRank: 6.82 |
Provides real-time physical verification of cells, blocks, and small IC designs. With strong interactivity for identifying and correcting layout errors, an ideal product for hand-crafting custom designs. |
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SoftRank: 6.82 |
A full-featured product supporting both interactive and batch operation modes and utilizes hierarchical processing for fast, efficient identification and correction of design rule errors in advanced designs. |
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SoftRank: 6.82 |
The mid-range custom block authoring physical layout tool, it supports the physical implementation of custom digital, mixed-signal, and analog designs at the device, cell, and block levels. |
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SoftRank: 6.82 |
Silicon-proven, full-chip physical design optimization system that improves manufacturability, yield, and performance, thus addressing the ever-important requirements for shorter time to convergence and shorter time to volume. It optimizes layout based on electrical constraints, manufacturing... |
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SoftRank: 6.82 |
Improves predictability, reduces cycle time, and increases yield by accelerating design signoff and facilitating multiple design turns per day for large 90nm and 65nm designs. Performance scales linearly and is limited only by the compute resources available. |
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SoftRank: 6.82 |
Dracula verification provides comprehensive and accurate verification for all design types and performs geometric, electrical, and connectivity checks, parasitic resistance and capacitance extraction. |
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SoftRank: 6.82 |
An option to Virtuoso® Spectre® Circuit Simulator, it provides fast, accurate simulations for RF and high-frequency ICs. |
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SoftRank: 6.82 |
Physical verification tool for interactive and batch mode, ensuring the layout connectivity of the physical design matches the logical design represented by the schematic or netlist before tapeout. |
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