HP/UX Computer-Aided Design (CAD) Software (41-50 of 75)

Comprehensive silicon analysis solution that provides all of the capabilities to verify that a physical layout meets manufacturing rules and matches the intended schematic for analog/mixed-signal designs.

This signal electromigration option to the Virtuoso Analog Design Environment addresses electromigration validation for analog designs with high-powered transistors or advanced process technologies.

The center piece of the full-chip integration function, it provides high-performance editing for full-chip finishing tasks and the capacity to handle your largest designs.

Performs automatic circuit sizing and optimization for custom digital, RF, and mixed-signal circuits -- employs the designer's simulator of choice to size, bias, and verify circuits interactively.

The physical layout migration tool that supports fast process and design rule migration of hard IP, custom digital designs, mixed-signal blocks, memories, and standard cell libraries.

The Fast-SPICE simulator that addresses the need for speed, capacity, design abstraction, and accuracy when verifying your design or system.

The mid-range custom block authoring physical layout tool, it supports the physical implementation of custom digital, mixed-signal, and analog designs at the device, cell, and block levels.

Improves predictability, reduces cycle time, and increases yield by accelerating design signoff and facilitating multiple design turns per day for large 90nm and 65nm designs. Performance scales linearly and is limited only by the compute resources available.

Comprehensive silicon analysis solution that provides all of the capabilities to verify that a physical layout meets manufacturing rules and matches the intended schematic for analog/mixed-signal high-frequency silicon designs.

The advanced design and simulation environment that sets the standard for fast, accurate design verification. It supports extensive exploration of multiple designs against their objective specifications.