HP/UX Computer-Aided Design (CAD) Software (1-10 of 75)

Handles high-density PCBs that require complex design rules, employing powerful, shape-based algorithms to make the most efficient use of the routing area.

Translates analog cell schematics into a full-custom optimized layout and capture the subtle electrical and geometrical constraints to enable analog layout reuse.

An option to Virtuoso® Spectre® Circuit Simulator, it provides fast, accurate simulations for RF and high-frequency ICs.

A state-of-the-art direct method circuit simulator that provides fast, accurate simulations for tough analog and mixed-signal circuits, as well as detailed transitor-level analysis in multiple domains.

Analyzes the combined impact of major noise sources including crosstalk, IR drop, and propagated noise on the design for custom digital circuits.

An easy-to-use mixed-signal simulation solution for the design and verification of the largest and most complex mixed-signal SoCs.

A constraint- and design-rule driven interactive and fully automatic shape-based router. It supports block authoring and chip authoring solutions for designs at any level of the hierarchy.

First Encounter provides a clear path to synthesize to a virtual prototype implementation including full-chip, routed wires—right at the beginning of the design cycle.

Encounter Timing System offers a consistent, integrated static timing analysis (STA) environment for place-and-route optimization and signoff verification.

The industry’s standard task-based environment for simulating and analyzing full-custom, analog, and RF IC designs. It also interfaces to popular third-party simulators.

SoC Encounter is a high-capacity, hierarchical, RTL-to-GDSII implementation system that combines RTL synthesis, silicon virtual prototyping, and full-chip implementation in a single system.

NanoRoute Ultra is an independent routing, optimization, verification, and chip-finishing solution with SMART routing and superthreading technology.

A full-featured product supporting both interactive and batch operation modes and utilizes hierarchical processing for fast, efficient identification and correction of design rule errors in advanced designs.

Fire & Ice QXC has redefined the accuracy requirements for cell-based digital designs—it is 2X more accurate as other extraction technologies and handles in-die process variations that often occur in advanced processes as 130nm and below.

The leading power grid verification solution and the first transistor-accurate power grid analysis product for use during physical design. It lets you apply production-proven IR drop analysis early so you can eliminate overdesign, gain flexibility for signal routing, and ease your timing closure...

Leading physical and electrical constraint-driven PCB layout system that addresses performance and a wide range of design, testability, and manufacturing challenges.

Streamlines IC package design and co-design through a complete constraint-driven physical design solution that supports virtually all packaging methods.

Physical verification tool for interactive and batch mode, ensuring the layout connectivity of the physical design matches the logical design represented by the schematic or netlist before tapeout.

Incisive Enterprise Specman Elite simplifies and speeds verification by automating test generation, capturing functional coverage, and enabling both code and behavioral re-use throughout the design cycle.

Incisive Verification Manager is an automated management system that guides the verification process and analyzes verification data, from planning to closure.

With native mixed-language support, dynamic assertion checking, transaction-level support, HDL analysis, and a complete debug environment, Incisive simulation verifies nanometer-scale ICs with speed and efficiency.

Extends the L family to provide higher levels of design assistance to the end-user, including 5x speed-up of common design tasks, constraint- and schematic-driven physical implementation, and other enhancements.

Comprises a complete constraint- and rules-driven package substrate layout environment that supports packaging methods, including PGA, BGA, MICRO-BGA, chip scale, and flip-chip/wirebond attach methods.

Provides a single top-level Virtuoso® schematic and simulation-driven environment for RF ICs, SiP RF module substrate, and embedded RF passive elements.

Fully integrates digital signal integrity analysis, interconnect extraction, and modeling with the physical SiP design environment.

Advanced library development tool that enables library creation and management by utilizing source-level data standards based on XML.

Provides a unique environment to explore, define, and optimize system connectivity and functionality between ICs, SiP substrates, and target PCBs

Allows electrical engineers to develop and embed optimum constraints during design creation phase. It’s tightly integrated with the proven simulation technology of Allegro Design Entry HDL.

Dracula verification provides comprehensive and accurate verification for all design types and performs geometric, electrical, and connectivity checks, parasitic resistance and capacitance extraction.

Provides real-time physical verification of cells, blocks, and small IC designs. With strong interactivity for identifying and correcting layout errors, an ideal product for hand-crafting custom designs.

The industy’s premier analog/mixed-signal extractor, providing high-speed parasitic extraction on full-chip layouts with silicon accuracy.

The design composition environment that delivers an extensive set of tools for custom IC design entry, from architectural definition to final structural implementations at the transistor level.

The high-end custom block authoring physical layout tool that supports the physical implementation of custom digital, mixed-signal, and analog designs at the device, cell, and block levels.

A comprehensive constraint-driven schematic design solution highly integrated within the Allegro platform with extensive simulation and verification options.

Provides an entry-level configuration of the industry's leading design system for complete front-to-back analog, RF, mixed-signal, and custom digital design.

This IR drop and power rail electromigration option to the Virtuoso Analog Design Environment extends the VoltageStorm family of power integrity products to analog designs.

The Incisive Palladium series offers acceleration and emulation technology that delivers up to 100x for simulation acceleration and 10,000x for in-circuit emulation with multi-user capability and optional acceleration-on-demand.

A combination of four fast, silicon-accurate simulation engines into a comprehensive solution that delivers the SPICE, FastSPICE, RF, and analog mixed-signal capabilities.

A suite of tools that provides the mechanism for linking your design and verification tools with the process you choose for your design, providing the key link between your design and your process.

The formal verification technology within Incisive Formal Verifier is used prior to testbench development and exposes corner-case bugs that are difficult or even impossible to find using simulation, acceleration, or emulation.

Comprehensive silicon analysis solution that provides all of the capabilities to verify that a physical layout meets manufacturing rules and matches the intended schematic for analog/mixed-signal designs.

This signal electromigration option to the Virtuoso Analog Design Environment addresses electromigration validation for analog designs with high-powered transistors or advanced process technologies.

The center piece of the full-chip integration function, it provides high-performance editing for full-chip finishing tasks and the capacity to handle your largest designs.

Performs automatic circuit sizing and optimization for custom digital, RF, and mixed-signal circuits -- employs the designer's simulator of choice to size, bias, and verify circuits interactively.

The physical layout migration tool that supports fast process and design rule migration of hard IP, custom digital designs, mixed-signal blocks, memories, and standard cell libraries.

The Fast-SPICE simulator that addresses the need for speed, capacity, design abstraction, and accuracy when verifying your design or system.

The mid-range custom block authoring physical layout tool, it supports the physical implementation of custom digital, mixed-signal, and analog designs at the device, cell, and block levels.

Improves predictability, reduces cycle time, and increases yield by accelerating design signoff and facilitating multiple design turns per day for large 90nm and 65nm designs. Performance scales linearly and is limited only by the compute resources available.

Comprehensive silicon analysis solution that provides all of the capabilities to verify that a physical layout meets manufacturing rules and matches the intended schematic for analog/mixed-signal high-frequency silicon designs.

The advanced design and simulation environment that sets the standard for fast, accurate design verification. It supports extensive exploration of multiple designs against their objective specifications.

The industry-standard base-level custom physical layout tool, it supports the physical implementation of custom digital, mixed-signal, and analog designs at the device, cell, and block levels.

Comprises the platform's most advanced configuration of design and analysis technologies, including expanded physical design capabilities and an enhanced simulation environment.

Industry's premier 3D full-chip parasitic extractor for fast and accurate implementation and validation of complex designs. It includes a full spectrum of technologies for all nanometer-scale design styles including RF, analog, mixed-signal, custom digital, and cell.

Encounter Test delivers advanced test solution from RTL to silicon providing fast time to market, minimizing the cost of test, enabling product quality, and speeding yield ramp.

Encounter Conformal offers the most comprehensive solution for equivalence checking, design-constraint management, and low-power design verification.

VoltageStorm is the leading power-grid verification solution, and the first transistor-accurate power-grid analysis product fast enough for use during physical design.

Enables layout designers to implement a SiP RF design that includes RF/analog die, embedded RF discretes, constraint-driven interconnect, and full SiP tapeout manufacturing preparation.

Enables fast and streamlined adoption of RF SiP design techniques by providing an integrated set of products built around proven methodologies that maximize SiP design productivity and predictability.

Provides an interactive, constraint-driven environment for creating and editing complex, multilayer, high-speed, high-density PCBs.

Streamlines complex IC package virtual prototyping and interconnect exploration, analysis, and modeling.

The industry’s first multi-style design creation environment. It provides the flexibility and power to create complex system designs using spreadsheets, traditional schematics, or HDL (Verilog®).

AutoSEA-SHOCK, allows you to predict transient and impulsive response (shock). Important applications include the shock response of military structures due to ballistic impact and explosions, as well as pyrotechnic shock response in aerospace vehicles.

Atrium: Project collaboration and CAD document sharing - architects & engineers

3Data Expet is a professional tool for repair, conversion and manipulation of 3D CAD data for Rapid Prototyping, 3D printing and simulation. You can recieve STL/VRML surface data from any source (Catia, ProE, 3D Studio Max, Alias...) and convert it into correct STL data.

The 3D ACIS® Modeler (ACIS) is Spatial's prominent 3D modeling development technology used by hundreds of software developers in 13 industries worldwide, including CAD/CAM/CAE, AEC, animation, and shipbuilding. ACIS provides some of the world's most recognized software developers and manufacturers...

The EnCapta product line extends popular CAD systems to capture all of the unique information associated with a product design. EnCapta enables engineers to efficiently manage this specialized data, share information with the extended enterprise, and connect engineering, manufacturing and business...

CATIA Model and Version Comparison + automatic orientation of surface lattice. With CATVER you are informed about changes! It dramatically reduces time-consuming, costly manual comparisons of geometric data and different versions in CATIA models.

Powerful standard parts management system for CATIA 2D and 3D. The standard part application can be started interactively from your CATIA window and you can simply load the requested component in CATIA.

The HOOPS/3d Application Framework (HOOPS/3dAF) consists of a highly optimized, integrated suite of industry leading software components. These provide an extensible, modular base architecture that enables the rapid design, development, and maintenance of high-performance, interactive 2d and 3d...

CAD/IQ is the world's premier CAD model quality testing tool. CAD/IQ locates and displays hidden errors and anomalies found in CAD models allowing problems to be detected and corrected before the model is released to downstream applications..

CAD model healing and repair software eliminates model rework.

Bi-directional STEP/ACIS 3D geometry translator

The Trimmed Surface Library (TSLib) provides a comprehensive suite of utilities for construction and interrogation of Trimmed Surfaces, Solids and Open Shells. Trimmed surfaces can be constructed from NURBS surfaces trimmed by model space (3-D) and/or parameter space (2-D) NURBS curves. The NURBS...

Glyph allows those I-DEAS users creating machined parts to easily add True Type Font geometry to their model files.

VisMockUp is a powerful, real-time, digital prototyping solution that enables users to detect and resolve design issues early in the development process. By combining advanced 2D and 3D visualization with sophisticated analyses of large product assemblies, this solution dramatically reduces or...