HP/UX Electrical Engineering Software (1-10 of 22)

BugHunter Pro is a graphical debugger and waveform viewer for controlling all popular VHDL and Verilog simulators, including VeriLogger Pro, VCS, ModelSim, NCSim, and ActiveHDL.

Verilogger Pro is a new type of simulation environment that combines all the features of a traditional Verilog simulator with the most powerful graphical test vector generation on the planet.

Timing Diagrammer Pro is a feature-laden timing diagram editor with an unbeatable price. Analyze your design in the early stages, before you have a schematic. Perform true full-range min/max timing analysis to eliminate all timing violations and race conditions. Timing Diagrammer Pro...

WaveFormer Pro is the perfect companion for any HDL simulator. Waveformer Pro generates simulation-ready HDL code from timing diagrams.

Debussy(r) is a complete, open debug system for Verilog and VHDL designs at the gate, RTL, and behavioral levels. It improves debug productivity by making complex designs easier to understand and by automating time-consuming debug tasks.

TestBencher Pro generates reactive Verilog, VHDL, and C++, models and test benches from language independent timing diagrams.

XFDTD uses the Finite Difference Time Domain method for providing full 3D electromagnetic analysis. Applications include antennas, wireless devices, biological effects of electromagnetic fields, special materials, and biomedical devices.

TimingDesigner® Professional is the industry-standard tool for authoring and analyzing timing diagrams and specifications.

The QuickBench® Verification Suite generates complete, reusable testbenches in VHDL or Verilog from graphical/HDL specifications. You can quickly and easily define the interface models, data, and sequences for your testbenches.

Sonnet Lite is a free, high frequency 3D planar electromagnetic (EM) analysis software package for electronic design engineers. It provides very accurate EM analysis of structures like circuit boards and integrated circuits.

State Navigator, the industry's first dedicated finite state machine (FSM) design, debug and verification environment for Verilog and VHDL designs, provides simultaneous debug of multiple, communicating state machines, behavioral FSM verification, static FSM verification and FSM coverage.

Verification Navigator, an integrated design verification environment that provides code coverage, test suite optimization, state machine coverage, and circuit activity analysis for Verilog, VHDL, and dual-language designs.

Breakthrough Compression Technology for the Semiconductor Industry - GDSII and MEBES Formats

The Vehicle Control Station (VCS) is a truly portable, fully integrated command, control and information system designed for the control of unmanned vehicles (UVs) and remote surveillance in both manned and unmanned applications.

ApsimRLGC is program to calculate the electrical parameters of a transmission line cross section. In particular it calculates the capacitance, inductance, resistance and conductance matrices associated with coupled lossy transmission lines.

ApsimSI can verify reflection and crosstalk noise along traces in layout designs using the most accurate lossy coupled transmission line simulator ApsimSPICE, fast transmission line parameter extractor ApsimRLGC and layout modeler ApsimLIF. ApsimSI is integrated with PCB and MCM CAD systems

As operating frequencies reach 1GHz and beyond noise introduced from the interconnect and power distribution system must accurately be accounted for in both PCB and IC design. Such noise can destroy timing budgets and cause functional failures. Simulation of these Signal Integrity issues has become...

MemChar provides complete solution for automation in memory characterization.

SpiceCut is a leading edge solution for automation in generating accurate critical path circuits for spice simulations.

MSIM is a characterization-oriented spice circuit simulator, which offers high speed and high accuracy for standard cell and memory characterization.

ApsimIBIS-LCR is a software tool for electrical characterization of various IC packaging technologies.

Standard-cell library development is made easy with ProGenesis, a comprehensive, generator-based tool suite that takes your SPICE netlist input and produces GDS layout for as many process technologies as you wish. ProGenesis retains all edits to your system, allowing you to incorporate design-rule...