Linux Electrical Engineering Software (1-10 of 13)

BugHunter Pro is a graphical debugger and waveform viewer for controlling all popular VHDL and Verilog simulators, including VeriLogger Pro, VCS, ModelSim, NCSim, and ActiveHDL.

Data book design environment with OLE & TDML support

Verilogger Pro is a new type of simulation environment that combines all the features of a traditional Verilog simulator with the most powerful graphical test vector generation on the planet.

Timing Diagrammer Pro is a feature-laden timing diagram editor with an unbeatable price. Analyze your design in the early stages, before you have a schematic. Perform true full-range min/max timing analysis to eliminate all timing violations and race conditions. Timing Diagrammer Pro...

WaveFormer Pro is the perfect companion for any HDL simulator. Waveformer Pro generates simulation-ready HDL code from timing diagrams.

Debussy(r) is a complete, open debug system for Verilog and VHDL designs at the gate, RTL, and behavioral levels. It improves debug productivity by making complex designs easier to understand and by automating time-consuming debug tasks.

XFDTD uses the Finite Difference Time Domain method for providing full 3D electromagnetic analysis. Applications include antennas, wireless devices, biological effects of electromagnetic fields, special materials, and biomedical devices.

Breakthrough Compression Technology for the Semiconductor Industry - GDSII and MEBES Formats

IPSA is an integrated suite of interactive-graphic steady state and dynamic analysis programs for the design and operational planning of electrical power systems.

The Vehicle Control Station (VCS) is a truly portable, fully integrated command, control and information system designed for the control of unmanned vehicles (UVs) and remote surveillance in both manned and unmanned applications.

MemChar provides complete solution for automation in memory characterization.

MSIM is a characterization-oriented spice circuit simulator, which offers high speed and high accuracy for standard cell and memory characterization.

Standard-cell library development is made easy with ProGenesis, a comprehensive, generator-based tool suite that takes your SPICE netlist input and produces GDS layout for as many process technologies as you wish. ProGenesis retains all edits to your system, allowing you to incorporate design-rule...