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<dc:creator><![CDATA[ SynaptiCAD ]]></dc:creator>
<dc:date>2005-05-23T15:10-05:00</dc:date>
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<description><![CDATA[ Engineering-Electrical Engineering: TimeGen is a timing diagram editor that helps a design engineer quickly and effectively draw timing diagrams and timing waveforms. ]]></description>
<category><![CDATA[ Engineering-Electrical Engineering ]]></category>
<dc:creator><![CDATA[ XFusion Software LLC ]]></dc:creator>
<dc:date>2005-04-10T23:56-05:00</dc:date>
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<description><![CDATA[ Engineering-Electrical Engineering: State Navigator the industry&#39 s first dedicated finite state machine (FSM) design debug and verification environment for Verilog and VHDL designs provides simultaneous debug of multiple communicating state machines behavioral FSM verification static FSM verification and FSM coverage. ]]></description>
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<dc:creator><![CDATA[ TransEDA ]]></dc:creator>
<dc:date>2005-01-30T00:54-05:00</dc:date>
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<description><![CDATA[ Engineering-Electrical Engineering: Verification Navigator an integrated design verification environment that provides code coverage test suite optimization state machine coverage and circuit activity analysis for Verilog VHDL and dual-language designs. ]]></description>
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<description><![CDATA[ Engineering-Electrical Engineering: EARS - Read view and run design rule checks on printed circuit board manufacturing information from CAD systems. ]]></description>
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<dc:creator><![CDATA[ Tibor Darvas Limited ]]></dc:creator>
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