<?xml version="1.0" encoding="iso-8859-1"?>
<rdf:RDF 
  xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
  xmlns:dc="http://purl.org/dc/elements/1.1/"
  xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
  xmlns:content="http://purl.org/rss/1.0/modules/content/"
  xmlns="http://purl.org/rss/1.0/"
>
<channel rdf:about="http://www.softscout.com/softscout/index.rss">
  <title>Computer-Aided Design (CAD) Software - SoftScout.com</title>
  <link>http://www.softscout.com</link>
  <description>Software Recently Added to SoftScout</description>
  <language>en-us</language>
  <items>
    <rdf:Seq>
    <rdf:li rdf:resource="http://www.softscout.com/softscout/softscout.nsf/0/C611FCE742F2D79C8525743B002BDC85" />
    <rdf:li rdf:resource="http://www.softscout.com/softscout/softscout.nsf/0/D816D1320A6F731E852572F90034E983" />
    <rdf:li rdf:resource="http://www.softscout.com/softscout/softscout.nsf/0/C6D38723C2F0AD3B8525721F0081A7E5" />
    <rdf:li rdf:resource="http://www.softscout.com/softscout/softscout.nsf/0/A96D5B687A475EE08525721F00818D6A" />
    <rdf:li rdf:resource="http://www.softscout.com/softscout/softscout.nsf/0/0A3DDA6AD6E0FAC58525721F0081688F" />
    <rdf:li rdf:resource="http://www.softscout.com/softscout/softscout.nsf/0/6B7F0DDD2F745FCC8525721F00814A8E" />
    <rdf:li rdf:resource="http://www.softscout.com/softscout/softscout.nsf/0/1E1EE23C6ED5D1728525721F00811FF2" />
    <rdf:li rdf:resource="http://www.softscout.com/softscout/softscout.nsf/0/DAAA5EBEB11284858525721F0080FD41" />
    <rdf:li rdf:resource="http://www.softscout.com/softscout/softscout.nsf/0/CF55064AF84462188525721F0080C64A" />
    <rdf:li rdf:resource="http://www.softscout.com/softscout/softscout.nsf/0/A20B198251A530B08525721F0080A5EA" />
    <rdf:li rdf:resource="http://www.softscout.com/softscout/softscout.nsf/0/097503518E56AA7E8525721F0080776E" />
    <rdf:li rdf:resource="http://www.softscout.com/softscout/softscout.nsf/0/46E4794B2E3221A98525721F00805150" />
    <rdf:li rdf:resource="http://www.softscout.com/softscout/softscout.nsf/0/88E838410B1708838525721F00801680" />
    <rdf:li rdf:resource="http://www.softscout.com/softscout/softscout.nsf/0/37623BFA24104AF68525721F007FE8AE" />
    <rdf:li rdf:resource="http://www.softscout.com/softscout/softscout.nsf/0/56475E6FB96843908525721F007FB5B9" />
    </rdf:Seq>
  </items>
</channel>
<item rdf:about="http://www.softscout.com/softscout/softscout.nsf/0/C611FCE742F2D79C8525743B002BDC85">
<link>http://www.softscout.com/softscout/softscout.nsf/0/C611FCE742F2D79C8525743B002BDC85</link>
<title><![CDATA[ GStarICAD ]]></title>
<description><![CDATA[ Engineering-Computer-Aided Design (CAD): GStarICAD is the geniune CAD drawing software based on IntelliCAD. ]]></description>
<category><![CDATA[ Engineering-Computer-Aided Design (CAD) ]]></category>
<dc:creator><![CDATA[ GreatStar Technology Co.,Ltd ]]></dc:creator>
<dc:date>2008-04-30T03:59-05:00</dc:date>
</item>

<item rdf:about="http://www.softscout.com/softscout/softscout.nsf/0/D816D1320A6F731E852572F90034E983">
<link>http://www.softscout.com/softscout/softscout.nsf/0/D816D1320A6F731E852572F90034E983</link>
<title><![CDATA[ Computers Expert ]]></title>
<description><![CDATA[ Engineering-Computer-Aided Design (CAD): Intota has built a proprietary network of thousands of leading technical and industry experts covering all areas of science and technology. ]]></description>
<category><![CDATA[ Engineering-Computer-Aided Design (CAD) ]]></category>
<dc:creator><![CDATA[ Intota.com ]]></dc:creator>
<dc:date>2007-06-13T05:37-05:00</dc:date>
</item>

<item rdf:about="http://www.softscout.com/softscout/softscout.nsf/0/C6D38723C2F0AD3B8525721F0081A7E5">
<link>http://www.softscout.com/softscout/softscout.nsf/0/C6D38723C2F0AD3B8525721F0081A7E5</link>
<title><![CDATA[ Allegro® System Architect ]]></title>
<description><![CDATA[ Engineering-Computer-Aided Design (CAD): The industry?s first multi-style design creation environment. It provides the flexibility and power to create complex system designs using spreadsheets traditional schematics or HDL (Verilog?). ]]></description>
<category><![CDATA[ Engineering-Computer-Aided Design (CAD) ]]></category>
<dc:creator><![CDATA[ Cadence Design Systems ]]></dc:creator>
<dc:date>2006-11-07T18:36-05:00</dc:date>
</item>

<item rdf:about="http://www.softscout.com/softscout/softscout.nsf/0/A96D5B687A475EE08525721F00818D6A">
<link>http://www.softscout.com/softscout/softscout.nsf/0/A96D5B687A475EE08525721F00818D6A</link>
<title><![CDATA[ Allegro® Design Workbench ]]></title>
<description><![CDATA[ Engineering-Computer-Aided Design (CAD): A comprehensive suite of products that combines design tool integration process control data management and library development and management in a single design environment. ]]></description>
<category><![CDATA[ Engineering-Computer-Aided Design (CAD) ]]></category>
<dc:creator><![CDATA[ Cadence Design Systems ]]></dc:creator>
<dc:date>2006-11-07T18:35-05:00</dc:date>
</item>

<item rdf:about="http://www.softscout.com/softscout/softscout.nsf/0/0A3DDA6AD6E0FAC58525721F0081688F">
<link>http://www.softscout.com/softscout/softscout.nsf/0/0A3DDA6AD6E0FAC58525721F0081688F</link>
<title><![CDATA[ Allegro® AMS Simulator ]]></title>
<description><![CDATA[ Engineering-Computer-Aided Design (CAD): Integrates the power of PSpice into the Allegro platform and provides advanced capabilities and options such as Monte-Carlo Sensitivity Smoke Analysis and Parametric plotter. ]]></description>
<category><![CDATA[ Engineering-Computer-Aided Design (CAD) ]]></category>
<dc:creator><![CDATA[ Cadence Design Systems ]]></dc:creator>
<dc:date>2006-11-07T18:33-05:00</dc:date>
</item>

<item rdf:about="http://www.softscout.com/softscout/softscout.nsf/0/6B7F0DDD2F745FCC8525721F00814A8E">
<link>http://www.softscout.com/softscout/softscout.nsf/0/6B7F0DDD2F745FCC8525721F00814A8E</link>
<title><![CDATA[ Allegro® PCB PI option ]]></title>
<description><![CDATA[ Engineering-Computer-Aided Design (CAD): An option to Cadence? Allegro PCB SI power integrity provides a design and analysis environment to develop clear reliable power delivery systems that work at all frequency ranges of interest. ]]></description>
<category><![CDATA[ Engineering-Computer-Aided Design (CAD) ]]></category>
<dc:creator><![CDATA[ Cadence Design Systems ]]></dc:creator>
<dc:date>2006-11-07T18:32-05:00</dc:date>
</item>

<item rdf:about="http://www.softscout.com/softscout/softscout.nsf/0/1E1EE23C6ED5D1728525721F00811FF2">
<link>http://www.softscout.com/softscout/softscout.nsf/0/1E1EE23C6ED5D1728525721F00811FF2</link>
<title><![CDATA[ Allegro® Design Entry CIS ]]></title>
<description><![CDATA[ Engineering-Computer-Aided Design (CAD): The most widely used schematic solution today. It has powerful component management capabilities and is integrated with Cadence PSpice? for analog design. ]]></description>
<category><![CDATA[ Engineering-Computer-Aided Design (CAD) ]]></category>
<dc:creator><![CDATA[ Cadence Design Systems ]]></dc:creator>
<dc:date>2006-11-07T18:30-05:00</dc:date>
</item>

<item rdf:about="http://www.softscout.com/softscout/softscout.nsf/0/DAAA5EBEB11284858525721F0080FD41">
<link>http://www.softscout.com/softscout/softscout.nsf/0/DAAA5EBEB11284858525721F0080FD41</link>
<title><![CDATA[ Allegro® Package SI L ]]></title>
<description><![CDATA[ Engineering-Computer-Aided Design (CAD): Streamlines complex IC package virtual prototyping and interconnect exploration analysis and modeling. ]]></description>
<category><![CDATA[ Engineering-Computer-Aided Design (CAD) ]]></category>
<dc:creator><![CDATA[ Cadence Design Systems ]]></dc:creator>
<dc:date>2006-11-07T18:28-05:00</dc:date>
</item>

<item rdf:about="http://www.softscout.com/softscout/softscout.nsf/0/CF55064AF84462188525721F0080C64A">
<link>http://www.softscout.com/softscout/softscout.nsf/0/CF55064AF84462188525721F0080C64A</link>
<title><![CDATA[ Allegro® PCB Design L, XL Series ]]></title>
<description><![CDATA[ Engineering-Computer-Aided Design (CAD): Provides an interactive constraint-driven environment for creating and editing complex multilayer high-speed high-density PCBs. ]]></description>
<category><![CDATA[ Engineering-Computer-Aided Design (CAD) ]]></category>
<dc:creator><![CDATA[ Cadence Design Systems ]]></dc:creator>
<dc:date>2006-11-07T18:26-05:00</dc:date>
</item>

<item rdf:about="http://www.softscout.com/softscout/softscout.nsf/0/A20B198251A530B08525721F0080A5EA">
<link>http://www.softscout.com/softscout/softscout.nsf/0/A20B198251A530B08525721F0080A5EA</link>
<title><![CDATA[ Allegro® PCB SI  ]]></title>
<description><![CDATA[ Engineering-Computer-Aided Design (CAD): Provides a scalable solution for pre- and post-route analysis of critical high-speed signals on PCB systems and is tightly integrated with the Allegro PCB design suites. ]]></description>
<category><![CDATA[ Engineering-Computer-Aided Design (CAD) ]]></category>
<dc:creator><![CDATA[ Cadence Design Systems ]]></dc:creator>
<dc:date>2006-11-07T18:25-05:00</dc:date>
</item>

<item rdf:about="http://www.softscout.com/softscout/softscout.nsf/0/097503518E56AA7E8525721F0080776E">
<link>http://www.softscout.com/softscout/softscout.nsf/0/097503518E56AA7E8525721F0080776E</link>
<title><![CDATA[ Cadence® RF SiP Methodology Kit ]]></title>
<description><![CDATA[ Engineering-Computer-Aided Design (CAD): Enables fast and streamlined adoption of RF SiP design techniques by providing an integrated set of products built around proven methodologies that maximize SiP design productivity and predictability. ]]></description>
<category><![CDATA[ Engineering-Computer-Aided Design (CAD) ]]></category>
<dc:creator><![CDATA[ Cadence Design Systems ]]></dc:creator>
<dc:date>2006-11-07T18:23-05:00</dc:date>
</item>

<item rdf:about="http://www.softscout.com/softscout/softscout.nsf/0/46E4794B2E3221A98525721F00805150">
<link>http://www.softscout.com/softscout/softscout.nsf/0/46E4794B2E3221A98525721F00805150</link>
<title><![CDATA[ Cadence®  SiP RF Layout ]]></title>
<description><![CDATA[ Engineering-Computer-Aided Design (CAD): Enables layout designers to implement a SiP RF design that includes RF/analog die embedded RF discretes constraint-driven interconnect and full SiP tapeout manufacturing preparation. ]]></description>
<category><![CDATA[ Engineering-Computer-Aided Design (CAD) ]]></category>
<dc:creator><![CDATA[ Cadence Design Systems ]]></dc:creator>
<dc:date>2006-11-07T18:21-05:00</dc:date>
</item>

<item rdf:about="http://www.softscout.com/softscout/softscout.nsf/0/88E838410B1708838525721F00801680">
<link>http://www.softscout.com/softscout/softscout.nsf/0/88E838410B1708838525721F00801680</link>
<title><![CDATA[ VoltageStorm® ]]></title>
<description><![CDATA[ Engineering-Computer-Aided Design (CAD): VoltageStorm is the leading power-grid verification solution and the first transistor-accurate power-grid analysis product fast enough for use during physical design. ]]></description>
<category><![CDATA[ Engineering-Computer-Aided Design (CAD) ]]></category>
<dc:creator><![CDATA[ Cadence Design Systems ]]></dc:creator>
<dc:date>2006-11-07T18:19-05:00</dc:date>
</item>

<item rdf:about="http://www.softscout.com/softscout/softscout.nsf/0/37623BFA24104AF68525721F007FE8AE">
<link>http://www.softscout.com/softscout/softscout.nsf/0/37623BFA24104AF68525721F007FE8AE</link>
<title><![CDATA[ Encounter® Conformal® technologies ]]></title>
<description><![CDATA[ Engineering-Computer-Aided Design (CAD): Encounter Conformal offers the most comprehensive solution for equivalence checking design-constraint management and low-power design verification. ]]></description>
<category><![CDATA[ Engineering-Computer-Aided Design (CAD) ]]></category>
<dc:creator><![CDATA[ Cadence Design Systems ]]></dc:creator>
<dc:date>2006-11-07T18:17-05:00</dc:date>
</item>

<item rdf:about="http://www.softscout.com/softscout/softscout.nsf/0/56475E6FB96843908525721F007FB5B9">
<link>http://www.softscout.com/softscout/softscout.nsf/0/56475E6FB96843908525721F007FB5B9</link>
<title><![CDATA[ Encounter® Test ]]></title>
<description><![CDATA[ Engineering-Computer-Aided Design (CAD): Encounter Test delivers advanced test solution from RTL to silicon providing fast time to market minimizing the cost of test enabling product quality and speeding yield ramp. ]]></description>
<category><![CDATA[ Engineering-Computer-Aided Design (CAD) ]]></category>
<dc:creator><![CDATA[ Cadence Design Systems ]]></dc:creator>
<dc:date>2006-11-07T18:14-05:00</dc:date>
</item>

</rdf:RDF>
