Cadence Chip Optimizer
Silicon-proven, full-chip physical design optimization system that improves manufacturability, yield, and performance, thus addressing the ever-important requirements for shorter time to convergence and shorter time to volume. It optimizes layout based on electrical constraints, manufacturing rules, and objectives.
Supported Technologies
AIX,
Solaris/Sun OS,
Linux
Software
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Pricing
- Unspecified -
http://www.cadence.com/company/cadence_worldwide/offices.aspx
800.746.6223, 408.954.1234
Resources
Additional Product Information
Silicon-proven, full-chip physical design optimization system that improves manufacturability, yield, and performance, thus addressing the ever-important requirements for shorter time to convergence and shorter time to volume. It optimizes layout based on electrical constraints, manufacturing rules, and objectives.