Computer-Aided Design (CAD) Software (11-20 of 161)

Encounter RTL Compiler delivers global synthesis for smaller, faster, and low-power chips in less time. It uses a unique set of patented global focus algorithms that maximize the performance of the most challenging designs.

A silicon-proven, 3D, hierarchical, grid-less, space-based, full-chip and block routing convergence system for advanced mixed-signal, analog, and custom digital designs at 65nm and below.

The formal verification technology within Incisive Formal Verifier is used prior to testbench development and exposes corner-case bugs that are difficult or even impossible to find using simulation, acceleration, or emulation.

A suite of tools that provides the mechanism for linking your design and verification tools with the process you choose for your design, providing the key link between your design and your process.

Provides a unique environment to explore, define, and optimize system connectivity and functionality between ICs, SiP substrates, and target PCBs

Fully integrates digital signal integrity analysis, interconnect extraction, and modeling with the physical SiP design environment.

Comprises a complete constraint- and rules-driven package substrate layout environment that supports packaging methods, including PGA, BGA, MICRO-BGA, chip scale, and flip-chip/wirebond attach methods.

The most widely used schematic solution today. It has powerful component management capabilities and is integrated with Cadence PSpiceŽ for analog design.

Provides real-time physical verification of cells, blocks, and small IC designs. With strong interactivity for identifying and correcting layout errors, an ideal product for hand-crafting custom designs.

A full-featured product supporting both interactive and batch operation modes and utilizes hierarchical processing for fast, efficient identification and correction of design rule errors in advanced designs.