Computer-Aided Design (CAD) Software (21-30 of 158)

With native mixed-language support, dynamic assertion checking, transaction-level support, HDL analysis, and a complete debug environment, Incisive simulation verifies nanometer-scale ICs with speed and efficiency.

Extends the L family to provide higher levels of design assistance to the end-user, including 5x speed-up of common design tasks, constraint- and schematic-driven physical implementation, and other enhancements.

Comprises a complete constraint- and rules-driven package substrate layout environment that supports packaging methods, including PGA, BGA, MICRO-BGA, chip scale, and flip-chip/wirebond attach methods.

Provides a single top-level VirtuosoŽ schematic and simulation-driven environment for RF ICs, SiP RF module substrate, and embedded RF passive elements.

Fully integrates digital signal integrity analysis, interconnect extraction, and modeling with the physical SiP design environment.

Advanced library development tool that enables library creation and management by utilizing source-level data standards based on XML.

Provides a unique environment to explore, define, and optimize system connectivity and functionality between ICs, SiP substrates, and target PCBs

Allows electrical engineers to develop and embed optimum constraints during design creation phase. It’s tightly integrated with the proven simulation technology of Allegro Design Entry HDL.

Dracula verification provides comprehensive and accurate verification for all design types and performs geometric, electrical, and connectivity checks, parasitic resistance and capacitance extraction.

Provides real-time physical verification of cells, blocks, and small IC designs. With strong interactivity for identifying and correcting layout errors, an ideal product for hand-crafting custom designs.