Computer-Aided Design (CAD) Software (21-30 of 161)

Incisive Verification Manager is an automated management system that guides the verification process and analyzes verification data, from planning to closure.

Allows electrical engineers to develop and embed optimum constraints during design creation phase. It’s tightly integrated with the proven simulation technology of Allegro Design Entry HDL.

Comprehensive silicon analysis solution that provides all of the capabilities to verify that a physical layout meets manufacturing rules and matches the intended schematic for analog/mixed-signal high-frequency silicon designs.

Translates analog cell schematics into a full-custom optimized layout and capture the subtle electrical and geometrical constraints to enable analog layout reuse.

The mid-range custom block authoring physical layout tool, it supports the physical implementation of custom digital, mixed-signal, and analog designs at the device, cell, and block levels.

Encounter Timing System offers a consistent, integrated static timing analysis (STA) environment for place-and-route optimization and signoff verification.

This IR drop and power rail electromigration option to the Virtuoso Analog Design Environment extends the VoltageStorm family of power integrity products to analog designs.

Encounter Conformal offers the most comprehensive solution for equivalence checking, design-constraint management, and low-power design verification.

Comprehensive silicon analysis solution that provides all of the capabilities to verify that a physical layout meets manufacturing rules and matches the intended schematic for analog/mixed-signal designs.

Leading physical and electrical constraint-driven PCB layout system that addresses performance and a wide range of design, testability, and manufacturing challenges.