QuickBench Verification Suite
The QuickBench® Verification Suite generates complete, reusable testbenches in VHDL or Verilog from graphical/HDL specifications. You can quickly and easily define the interface models, data, and sequences for your testbenches.
English
Supported Technologies
HP/UX,
Solaris/Sun OS,
Windows XP/2000/NT
Software
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Pricing
Users (# of seats), Server, Module, Other
call
sales@chronology.com
425-869-4227
Additional Product Information
The QuickBench® Verification Suite provides high-level testbench specification capability. It supports effective design of both timing and functional waveform specifications for the "design-under-test" (DUT), a powerful environment for the generation of transactions and data to exercise and test the DUT, and a design flow manager to manage the creation of the testbench.;The QuickBench Verification Suite consists of 3 components:;QB-Modeler - a tool for building bus-functional models from timing diagram interface specifications.;QB-Sequencer - a tool for generating verification sequences that orchestrate the testbench.;QB-Manager - a tool for assembling models, the netlist, and other resources into a simulatable testbench.