TestBencher Pro
TestBencher Pro generates reactive Verilog, VHDL, and C++, models and test benches from language independent timing diagrams.
Supported Technologies
Windows 95/98/ME,
Windows XP/2000/NT ,
HP/UX,
Solaris/Sun OS
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Pricing
- Unspecified -
$17000 to $25000
sales@syncad.com
800-804-7073
Additional Product Information
SynaptiCAD’s TestBencher Pro dramatically reduces the time necessary to develop test suites by generating model code from language independent graphical timing diagrams. Quickly generate bus-functional models using features like sequence recognition, protocol checking, random data generation, automatic signal extraction from HDL models, parameterization of state and timing values, and stability or transition checkers. TestBencher also automates the build process by controlling external simulators and compilers through its graphical interface. TestBencher handles all of the details of creating make files and issuing commands to dynamically link library or byte code, allowing you to focus on the design and operation of the model. SynaptiCAD also offers Verilog simulation and timing diagram visualization tools.