RAM Designer
A unique program for the fast design, analysis and optimization of high performance SRAM arrays.
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English
Supported Technologies
AIX,
HP/UX,
Solaris/Sun OS
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Pricing
- Unspecified -
info@oea.com
408-738-5972
Additional Product Information
RAM Designer is a program for the design, analysis and optimization ;of SRAM arrays. Using the SPICE circuit of the RAM cell and control ;circuits, the designer can quickly configure and analyze any RAM cell;location. In one analysis mode, the read and write cycle timing can;be analyzed in detail for key memory locations in the array. Speed ;of operation can be calculated and what-if analysis can be done by ;substituting in other circuits for the sense amplifier, data bus ;driver, word line driver, or pre-charge cells. In another analysis ;mode, crosstalk and power line noise can be analyzed. When compared ;to manual methods, RAM Designer drastically reduces the time required;and eliminates the errors encountered with creating and analyzing RAM ;array SPICE runs. Linked closely with SPICE, waveforms at critical ;points in the circuit are easily displayed and timing given. RAM ;Designer takes cell SPICE circuits from the OEA CELL-AN tool or any ;other RC extraction tool.