RING Designer
A program for optimizing the design of VLSI power distribution I/O rings. Common problems of ground bounce and simultaneous switching noise are easily debugged and solutions found by fast turn around what-if analysis.
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English
Supported Technologies
AIX,
HP/UX,
Solaris/Sun OS
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Pricing
- Unspecified -
info@oea.com
408-738-5972
Additional Product Information
RING Designer is a program that works with the OEA NET-AN program ;for optimizing the design of VLSI power distribution I/O rings. ;Common problems of ground bounce and simultaneous switching noise ;are easily debugged and solutions found by fast turn around what-if ;analysis. RING Designer allows for fast changes in ring width, pad ;locations, by-pass capacitor value selection and location, and buffer ;size selection and locations to resolve problems.;RING Designer allows the user to easily specify the full SPICE ;circuit parameters of the planned ring design including I/O buffer ;SPICE circuits, power ring sizes, and locations of by-pass capacitors, ;voltage supply pads and I/O buffers. Using the OEA 3-D Extraction ;tool, NET-AN, a full RCLK SPICE circuit of the ring is created ;including SPICE commands to measure buffer currents and delays. ;Also, package parasitics and PCB parasitics can be extracted using ;the OEA HENRY and METAL programs and then included in the ring ;simulation. Once the complete circuit is specified, SPICE is run ;and the resulting transient analysis is given for various switching ;vectors.;By calculating the optimal number of VDD/VSS supply pads, RING ;Designer can save package pins and even allow a smaller pin count ;package to be used in some cases. Cost trade-offs are made easily ;because the PCB, package and chip rings are modeled together.