Cadence Design Systems Vendor Profile

Integrates the power of PSpice into the Allegro platform and provides advanced capabilities and options such as Monte-Carlo, Sensitivity, Smoke Analysis and Parametric plotter.

The most widely used schematic solution today. It has powerful component management capabilities and is integrated with Cadence PSpice® for analog design.

Allows electrical engineers to develop and embed optimum constraints during design creation phase. It’s tightly integrated with the proven simulation technology of Allegro Design Entry HDL.

A comprehensive constraint-driven schematic design solution highly integrated within the Allegro platform with extensive simulation and verification options.

A comprehensive suite of products that combines design tool integration, process control, data management, and library development and management in a single design environment.

Streamlines IC package design and co-design through a complete constraint-driven physical design solution that supports virtually all packaging methods.

Streamlines complex IC package virtual prototyping and interconnect exploration, analysis, and modeling.

Provides an interactive, constraint-driven environment for creating and editing complex, multilayer, high-speed, high-density PCBs.

Leading physical and electrical constraint-driven PCB layout system that addresses performance and a wide range of design, testability, and manufacturing challenges.

Advanced library development tool that enables library creation and management by utilizing source-level data standards based on XML.

An option to Cadence® Allegro PCB SI, power integrity provides a design and analysis environment to develop clear, reliable power delivery systems that work at all frequency ranges of interest.

Handles high-density PCBs that require complex design rules, employing powerful, shape-based algorithms to make the most efficient use of the routing area.

Provides a scalable solution for pre- and post-route analysis of critical high-speed signals on PCB systems and is tightly integrated with the Allegro PCB design suites.

The industry’s first multi-style design creation environment. It provides the flexibility and power to create complex system designs using spreadsheets, traditional schematics, or HDL (Verilog®).

A full-featured product supporting both interactive and batch operation modes and utilizes hierarchical processing for fast, efficient identification and correction of design rule errors in advanced designs.

Physical verification tool for interactive and batch mode, ensuring the layout connectivity of the physical design matches the logical design represented by the schematic or netlist before tapeout.

The industy’s premier analog/mixed-signal extractor, providing high-speed parasitic extraction on full-chip layouts with silicon accuracy.

Silicon-proven, full-chip physical design optimization system that improves manufacturability, yield, and performance, thus addressing the ever-important requirements for shorter time to convergence and shorter time to volume. It optimizes layout based on electrical constraints, manufacturing...

Industry's premier 3D full-chip parasitic extractor for fast and accurate implementation and validation of complex designs. It includes a full spectrum of technologies for all nanometer-scale design styles including RF, analog, mixed-signal, custom digital, and cell.

Provides a unique environment to explore, define, and optimize system connectivity and functionality between ICs, SiP substrates, and target PCBs

Comprises a complete constraint- and rules-driven package substrate layout environment that supports packaging methods, including PGA, BGA, MICRO-BGA, chip scale, and flip-chip/wirebond attach methods.

Fully integrates digital signal integrity analysis, interconnect extraction, and modeling with the physical SiP design environment.

Enables layout designers to implement a SiP RF design that includes RF/analog die, embedded RF discretes, constraint-driven interconnect, and full SiP tapeout manufacturing preparation.

Improves predictability, reduces cycle time, and increases yield by accelerating design signoff and facilitating multiple design turns per day for large 90nm and 65nm designs. Performance scales linearly and is limited only by the compute resources available.

Enables fast and streamlined adoption of RF SiP design techniques by providing an integrated set of products built around proven methodologies that maximize SiP design productivity and predictability.

Provides a single top-level Virtuoso® schematic and simulation-driven environment for RF ICs, SiP RF module substrate, and embedded RF passive elements.

A silicon-proven, 3D, hierarchical, grid-less, space-based, full-chip and block routing convergence system for advanced mixed-signal, analog, and custom digital designs at 65nm and below.

Provides real-time physical verification of cells, blocks, and small IC designs. With strong interactivity for identifying and correcting layout errors, an ideal product for hand-crafting custom designs.

Dracula verification provides comprehensive and accurate verification for all design types and performs geometric, electrical, and connectivity checks, parasitic resistance and capacitance extraction.

Encounter Conformal offers the most comprehensive solution for equivalence checking, design-constraint management, and low-power design verification.

Encounter RTL Compiler delivers global synthesis for smaller, faster, and low-power chips in less time. It uses a unique set of patented global focus algorithms that maximize the performance of the most challenging designs.

Encounter Test delivers advanced test solution from RTL to silicon providing fast time to market, minimizing the cost of test, enabling product quality, and speeding yield ramp.

Encounter Timing System offers a consistent, integrated static timing analysis (STA) environment for place-and-route optimization and signoff verification.

Fire & Ice QXC has redefined the accuracy requirements for cell-based digital designs—it is 2X more accurate as other extraction technologies and handles in-die process variations that often occur in advanced processes as 130nm and below.

First Encounter provides a clear path to synthesize to a virtual prototype implementation including full-chip, routed wires—right at the beginning of the design cycle.

Incisive Enterprise Specman Elite simplifies and speeds verification by automating test generation, capturing functional coverage, and enabling both code and behavioral re-use throughout the design cycle.

The Incisive Palladium series offers acceleration and emulation technology that delivers up to 100x for simulation acceleration and 10,000x for in-circuit emulation with multi-user capability and optional acceleration-on-demand.

The Incisive Xtreme Series provides simulation, acceleration and emulation technology that improves design team productivity and automates the verification process, from executable plan to closure.

The formal verification technology within Incisive Formal Verifier is used prior to testbench development and exposes corner-case bugs that are difficult or even impossible to find using simulation, acceleration, or emulation.

With native mixed-language support, dynamic assertion checking, transaction-level support, HDL analysis, and a complete debug environment, Incisive simulation verifies nanometer-scale ICs with speed and efficiency.

Incisive Verification Manager is an automated management system that guides the verification process and analyzes verification data, from planning to closure.

NanoRoute Ultra is an independent routing, optimization, verification, and chip-finishing solution with SMART routing and superthreading technology.

Analyzes the combined impact of major noise sources including crosstalk, IR drop, and propagated noise on the design for custom digital circuits.

SoC Encounter is a high-capacity, hierarchical, RTL-to-GDSII implementation system that combines RTL synthesis, silicon virtual prototyping, and full-chip implementation in a single system.

Comprises the platform's most advanced configuration of design and analysis technologies, including expanded physical design capabilities and an enhanced simulation environment.

Provides an entry-level configuration of the industry's leading design system for complete front-to-back analog, RF, mixed-signal, and custom digital design.

Extends the L family to provide higher levels of design assistance to the end-user, including 5x speed-up of common design tasks, constraint- and schematic-driven physical implementation, and other enhancements.

The physical layout migration tool that supports fast process and design rule migration of hard IP, custom digital designs, mixed-signal blocks, memories, and standard cell libraries.

Translates analog cell schematics into a full-custom optimized layout and capture the subtle electrical and geometrical constraints to enable analog layout reuse.

Performs automatic circuit sizing and optimization for custom digital, RF, and mixed-signal circuits -- employs the designer's simulator of choice to size, bias, and verify circuits interactively.