TransEDA Vendor Profile

State Navigator, the industry's first dedicated finite state machine (FSM) design, debug and verification environment for Verilog and VHDL designs, provides simultaneous debug of multiple, communicating state machines, behavioral FSM verification, static FSM verification and FSM coverage.

Verification Navigator, an integrated design verification environment that provides code coverage, test suite optimization, state machine coverage, and circuit activity analysis for Verilog, VHDL, and dual-language designs.